1. Field of the Invention
This invention relates to the field of video circuits. More particularly, this invention relates to a circuit for detecting synchronizing pulses embedded in composite waveforms of a video signal.
2. Description of the Related Art
FIG. 1 illustrates components of a composite video waveform. The composite video waveform contains: a horizontal sync pulse or sync tip used for receiver scan timing; a xe2x80x9cbreezewayxe2x80x9d where the level is a reference for video intensity; a color burst which is a series of sinewaves at a very precise frequency and phase, used as a color reference; a back porch which is a level reference similar to the breezeway occurring after the color burst segment; and the picture occurring after the back porch, the picture being any possible signal up to a maximum level, and whose content is unpredictable to receiver electronics.
The video receiver systems must discover timing details from the sync tip. Unfortunately, the sync tip almost never has a known DC level. In fact, most composite signals are AC coupled and the average DC level varies unpredictably with picture content.
One method for providing a video signal timing reference is to use a circuit which uses the most negative going feature of the composite signal as a reference level. The composite video signal standard which is predominantly used in North America, the National Television Systems Committee (NTSC) standard, was designed to enable such a reference level to be set approximately 50 years ago.
A prior art circuit for setting a reference level at the most negative feature of a composite waveform is the clamping circuit shown in FIG. 2. The circuit includes a capacitor 200 having an input receiving the composite video signal input, and an output providing the composite video signal with its most negative voltage clamped to 0 volts. The circuit further includes a diode 202 and current sink 204 connecting the output of the capacitor 200 to ground. The diode 202 is assumed to be ideal so that it generates no DC offset. The current sink 204 provides a small pull down current IPULLDOWN to discharge the capacitor 200 and allow the clamped output signal to follow the varying content of the composite input.
A clamped output signal from the circuit of FIG. 2 is shown in FIG. 3. As shown in FIG. 3, the diode of FIG. 2 forces the capacitor coupled composite video signal""s most negative voltage, here the sync tip voltage (VTIP), to ground level. Because the composite video signal provides transient currents, clamping may distort the composite signal and may be an undesirable method.
To provide a synchronization (sync) timing signal, the clamped output of the circuit of FIG. 2 is provided to a first terminal of comparator 400 shown in FIG. 4, while a DC offset voltage is provided to the second terminal of comparator 400. The sync timing signal is generated when the comparator output transitions. A DC voltage offset generator 402 provides the DC offset voltage at a desired xe2x80x9cslice levelxe2x80x9d (VSLICE), as shown in FIG. 3, so that the sync timing signal is generated on an edge of the sync pulse at the voltage VSLICE approximately midway between the sync tip voltage level VTIP and the breezeway voltage level.
The present invention provides a circuit for following variations of the composite video signal, rather than clamping the most negative voltage of the composite video signal.
The present invention includes a negative peak detector with an input receiving the composite video signal and an output coupled to a first input of a first amplifier the first amplifier functioning as a comparator. The second input of the comparator receives the composite signal, and the output of the comparator provides a synchronization timing signal.
In one embodiment, the present invention further provides buffering at the input and output of the negative peak detector. Buffering is provided to the input with a second amplifier having a noninverting input receiving the composite video signal. The inverting input of the second amplifier is connected to a first terminal of a diode of the peak detector and also to a current source in the negative peak detector. The output of the second amplifier is connected to the second end of the diode of the negative peak detector. The second amplifier serves to buffer the composite video signal from the current source. Buffering at the output of the negative peak detector is provided by a third amplifier connected in a voltage follower configuration between the output of the negative peak detector and the comparator.
In one embodiment, the present invention also includes a voltage slice level offset generator connecting the output of the negative peak detector to the comparator. The slice level offset generator includes a sample and hold circuit and a resistor divider. The sample and hold circuit is configured to sample the composite video signal during the breezeway segment, color burst segment, or back porch segments of the composite video signal, or any combination of the segments. The output of the sample and hold circuit then provides a sample of these segments VREF to a first end terminal of the resistor divider. The second end terminal of the resistor divider is driven by the buffered output of the negative peak detector which provides a synchronization tip voltage signal VTIP, and the center terminal of the resistor divider is provided to the first input of the comparator. The comparator output can then provide a timing signal transitioning at a point VSLICE on the composite signal half way between VTIP and VREF.
In another embodiment in accordance with the present invention, circuitry is configured to reduce amplifier DC offset which can cause errors in a perceived VSLICE level. The circuitry includes a first amplifier which receives the composite video signal and is connectable by switches in one of three positions TCOMP, TTIP and TH. In the TCOMP position the first amplifier acts as a comparator with no feedback to compare the value VSLICE+VTIP with the composite video signal. VSLICE is set between VTIP and VREF based on values stored on capacitors in the circuit. The TCOMP position is used prior to the negative going synchronization tip edge of the composite video signal. After the negative going edge of the synchronization tip, the circuit is set in the TTIP position. In the TTIP position, the output of the first amplifier is disconnected from providing the synchronization timing output, and is connected to provide buffering for a negative peak detector to store TTIP on a capacitor. After the synchronization tip, during the breezeway, color burst or back porch segments of the composite video signal, or during a desired combination of these segments the circuit is connected in the TH position. In the TH position, the first amplifier forms part of a sample and hold circuit for storing a value VREF on a capacitor. After the desired period for TH, the circuit is again connected in the TCOMP position for detection of the next negative going synchronization tip edge.